1. Field of the Invention
The present invention relates generally to register files of microprocessors, and more particularly to register files that support multiple register sizes simultaneously.
2. Description of Related Art
As processors have become more powerful, the size of a data unit processed by such processors has continually increased. For example, some of the earlier processors included register files where each register entry stored a byte of data. The register size in register files in some processors is sixty-four bits for each register.
Typically, when a new processor is introduced, the processor is configured to process computer code that was written for earlier processors with smaller register sizes as well as computer code written for the largest register size available in the new processor, i.e., backward compatibility for computer programs is maintained in the new processor. FIG. 1A is an example of a register file 100 in which the size of a register has doubled from one generation of a processor to the next generation of that processor. For example, the older processor utilized thirty-two thirty-two bit registers, f0 to f31. The new processor utilizes thirty-two sixty-four bit registers d0 to d31.
As shown in FIG. 1A, the least significant thirty-two bits of register d0 is register f0 and the most significant thirty-two bits of register d0 is register f1. Thus, register d0 includes register f0 and register f1. Herein, register f1 is referred to as the twin of register f0. Each of registers d0 to d15 includes two thirty-two bit registers and so each of registers d0 to d15 includes twin registers.
The thirty-two bit register in the most significant bits of the sixty-four bit register is referred to as the evil twin of the thirty-two bit register in the least significant bits of that sixty-four bit register. Use of register file 100 for executing instructions that use both thirty-two bit and sixty-four bit registers can lead to a problem, which is referred to as the “evil-twin” problem.
If two instructions are coupled through a thirty-two bit register in the most significant bits for a sixty-four bit register, i.e., coupled by the evil-twin register, the processor normally does not detect the coupling. Thus, incorrect results may be obtained as a result of the evil-twin problem.
As an example, the comparators for instructions using sixty-four bit operands do not detect an instruction using the thirty-two-most significant bits of the sixty-four bit register as a destination. FIG. 1B is a segment of a computer program 150 that includes instructions that are coupled but the coupling is not detected by the comparators and so computer program 150 suffers from the evil-twin problem.
In FIG. 1B, load instruction ld loads a value in register f1, which is the thirty-two most significant bits of register d0 and is the evil-twin register. Floating pointing double precision add instruction fdadd, in the next line, adds the value in register d0 to the value in register d4 and places the resulting value in register d8. Register d0 is a sixty-four bit register and so includes any value in register f1, as indicated in FIG. 1A.
However, the comparators, which are used in determining instructions on which floating point double precision add instruction fdadd depends, do not detect the dependence of floating point double precision add instruction fdadd on the result of load instruction ld in evil-twin register f1. Thus, the floating point double precision add instruction fdadd could be performed before load instruction ld completed. In this case, the accuracy of the result of the floating point double precision add instruction fdadd is unknown, and is most likely incorrect because the result of instruction ld is not in evil-twin register f1.
Similarly, sixty-four bit register d8 includes thirty-two bit register f17, also as shown in FIG. 1A. Floating point add instruction fadd adds the value in register f15 to the value in evil-twin register f17 and places the resulting value in register f23. However, register f17 does not include the correct value until after floating point double precision add instruction fdadd completes.
The dependence of floating point add instruction fadd on the result of floating point double precision add instruction fdadd is not detected by the comparators. Thus, floating point add instruction fadd could be performed before floating point double precision add instruction fdadd completed. In this case, the accuracy of the result of floating point add instruction fadd is unknown, and is most likely incorrect because the result of instruction fdadd is not in evil-twin register f17.
In each of these instances, the problem is the inability of the processor to detect the dependence of an instruction on a value in an evil-twin register. As noted, this problem is referred to as the evil-twin problem.
In this example, each of registers f1, f3, . . . is the referred to as the evil twin of registers f0, f2, respectively. This evil-twin problem has been accepted because the mapping of the different sized registers to the same register file minimizes the area required by the register file while permitting execution of different generations of computer code on a processor. Moreover, to avoid the evil-twin problem, some processors, for example, prohibit launching a double precision instruction until all single precision instructions have completed, and conversely. The delay in launching stalls the pipeline until execution is completed for the one set of instructions.